10. CACHE Instructions
If the IState is 1 (Valid), and the PA of the CACHE instruction matches the Tag from the instruction cache tag array, the IState bit of the entry is written to 0 (Invalid) and the IState parity bit is written to 0.
The LRU bit does not change.
Parity error is checked.
Hit CacheOps can cause cache error exceptions if they check ECC or parity bits.
